1. Field of the Invention
The present invention relates generally to liquid crystal display (LCD) drivers, and more particularly, to digital signal control circuits and methods for conserving power and minimizing layout space for use with LCD drivers.
2. Background Art
LCD displays are commonly used for applications such as computer display monitors, television monitors, and other devices for displaying text, photo, video, or other types of information. LCD displays may be made of certain types of liquid crystal display material, as is well understood by those familiar with display technologies. In typical LCDs, liquid crystal material fills the space or gap between a pair of row and column substrates to form a cell or pixel. Perpendicular row and column electrodes are patterned on to the respective substrates to permit an electric potential to be selectively created at particular points (i.e., cells) on the display to alter the appearance of the liquid crystal material. Row and column (data) drivers are utilized to address selected cells.
Each of these LCD (row and column) drivers receive an n-bit digital input data that is used to select one out of 2n voltage levels to be provided to the desired row or column electrodes. FIG. 1 illustrates a conventional LCD driver circuit where n is equal to 2. The 2-bit input data is processed by a 2xc3x974 decoder for selecting one of the four digital lines {D00, D01, D10, D11} to pass one of the four voltage levels {V0, V1, V2, V3} to an output circuit and then on to the desired electrode. An optional sample and hold circuit designated SandH is provided at the output for boosting the signal strength of the output analog voltage.
FIG. 2 illustrates a known signal-line routing scheme based on the conventional LCD driver in FIG. 1. The four voltage lines carrying the voltage levels {V0, V1, V2, V3} are M2 (metal-2) lines, and the four decoded lines for carrying the decoded digital signals are M1 (metal-1) lines. The M2 and M1 lines are arranged perpendicular to each other. The output is used for driving one column of the LCD cells. The M2 lines that carry the analog voltages {V0, V1, V2, V3} extend further from what is illustrated in FIG. 2, and are used to drive other columns of LCD cells via other decoders.
FIG. 3 illustrates the LCD driver circuit and routing scheme that is similar to a commercial LCD driver distributed by NEC Corp., and known as the xe2x80x9cNEC uPD16632xe2x80x9d. For simplicity, only n=2 bits are shown in FIG. 3 to select one of four voltage levels for output driving. There are 2n (i.e., 4) digital signal lines {a, a-bar, b, b-bar} that are used for controlling a matrix of 2nxc3x972n (i.e., 16) pass transistors, for selecting one of 2n (i.e., 4) voltage levels as the output voltage. As compared with FIGS. 1 and 2, no decoder is used to process the digital input data. The voltage levels {V0, V1, V2, V3} are carried by metal lines that are fabricated by a metal-1 or metal-2 layer. The 2n digital signal lines are carried by polysilicon lines that are perpendicular to the metal lines. Due to the column pitch and metal/polysilicon line pitch considerations, even though the number of pass transistors {M00, M01, . . . , M33} used is significantly higher than illustrated in FIGS. 1 and 2, the actual layout is not necessarily larger, and can actually be smaller, than the layout in FIGS. 1 and 2.
The pass transistors in FIG. 3 that have been circled (i.e., M00, M02, M10, M13, M21, M22, M31, M33} are depletion implanted to a negative threshold voltage so that they are always turned xe2x80x9cONxe2x80x9d regardless of the voltage level (i.e., high or low) of each digital signal line {a, a-bar, b, b-bar}. In other words, these depletion implanted transistors operate as xe2x80x9cdon""t carexe2x80x9d transistors that pass whatever voltages are transmitted therethrough. The negative threshold voltage of these depletion implanted pass transistors enables the use of polysilicon lines as both the digital signal lines and the gates of those pass transistors to achieve savings in layout. This will become apparent by viewing the layout shown in FIG. 4.
FIG. 4 is a top view of a layout that is similar to the layout of the NEC uPD16632 of FIG. 3. In this example, n=3 bits are used. As a result, there are 2n (i.e., 6) digital signal lines {a, a-bar, b, b-bar, c, c-bar}, and 2n (i.e., 8) voltage levels {V0, V1, V2, V3, V4, V5, V6, V7}. These eight voltage levels are carried by eight active regions labeled AR that include diffusion regions (e.g., n+ implanted). As known in the art, a diffusion region is an n+ or p+ implanted and later diffused region (due to thermal cycles) in an active region surrounded by field oxide isolation. These eight voltage levels {V0, V1, V2, V3, V4, V5, V6, V7} are divided into even-numbered voltage levels {V0, V2, V4, V6} at one side of the layout of FIG. 4, and odd-numbered voltage levels {V1, V3, V5, V7} at another side of the layout of FIG. 4. A DAC output node is coupled to the action regions AR through metal-1 lines and metal-to-diffusion contacts. The six digital signal lines {a, a-bar, b, b-bar, c, c-bar} are carried by polysilicon lines, with six digital signal lines {a, a-bar, b, b-bar, c, c-bar} on a different side of the layout. A pass transistor PT is formed where each polysilicon line {a, a-bar, b, b-bar, c, c-bar} crosses an active region AR, with the portion of the polysilicon overlapping the active region AR as the gate for the pass transistor. Again, each circled pass transistor is depletion implanted through the use of a mask.
As shown in FIG. 4, the voltage levels {V0, V1, V2, V3, V4, V5, V6, V7} increase monotonously from V0 through V7. For example, V0 will be selected as the output voltage if {a}, {b} and {c} are all digital xe2x80x9clowxe2x80x9d (i.e., 0). This is because the {a}, {b} and {c} lines overlap depletion implanted transistors at the voltage level for V0 (i.e., the voltage V0 passes through), and the {a-bar}, {b-bar} and {c-bar} lines will carry a xe2x80x9chighxe2x80x9d signal (i.e., a=0, b=0, c=0) to pass the voltage level V0 to the DAC output. As a further example, V1 will be selected as the output voltage if {a} and {b} are all digital xe2x80x9clowxe2x80x9d (i.e., 0), and {c} is digital xe2x80x9chighxe2x80x9d. This is because the {a}, {b} and {c-bar} lines overlap depletion implanted transistors at the voltage level for V1 (i.e., the voltage V1 passes through), and the {a-bar}, {b-bar} and {c} lines will carry a xe2x80x9chighxe2x80x9d signal (i.e., a=0, b=0, c 32 1) to pass the voltage level V1 to the DAC output. As yet another example, V6 will be selected as the output voltage if {c} is digital xe2x80x9clowxe2x80x9d (i.e., 0), and {a} and {b} are both digital xe2x80x9chighxe2x80x9d. This is because the {a-bar}, {b-bar} and {c} lines overlap depletion implanted transistors at the voltage level for V6 (i.e., the voltage V6 passes through), and the {a}, {b} and {c-bar} lines will carry a xe2x80x9chighxe2x80x9d signal (i.e., a=1, b=1, c=0) to pass the voltage level V6 to the DAC output. Using the same methodology, and given the layout illustrated in FIG. 4, the corresponding digital signals and selected voltage levels are as follows:
Unfortunately, the layouts in FIGS. 3 and 4 suffer from the drawbacks that they take up much space, and require a large amount of power for driving the circuit.
It is an object of the present invention to provide an improved digital signal control circuit that conserves power.
It is another object of the present invention to provide an improved digital signal control circuit that conserves layout space.
It is a further object of the present invention to provide an improved digital signal control circuit that has fewer or reduced signal lines.
Improvements are needed to reduce the number of poly lines and pass transistors to save both layout space and power. As the gate of each pass transistor becomes a load for the {a, a-bar, b, b-bar, c, c-bar} signal driving lines, reduction of the poly lines and pass gates will reduce power consumption.
In accordance with the foregoing and other objectives of the invention, the present invention provides a driver circuit for use in driving displays, the circuit having an input receiving a digital input data having n bits for selecting one of a plurality of voltage levels for driving the circuit. The circuit also has an output, a plurality of digital signal lines coupled to the digital input data, and a plurality of active regions coupled to a first side of the output. Each of the plurality of active regions is coupled to a separate voltage level. The circuit further includes a plurality of pass transistors at a first subset of locations where the plurality of digital signal lines overlap the plurality of active regions, and a plurality of depletion-implanted transistors at a second subset of locations where the plurality of digital signal lines overlap the plurality of active regions. It is also possible to provide a second plurality of active regions coupled to a second side of the output.
In one embodiment of the present invention, the number of the plurality of digital signal lines on one side of the output is an odd number, and can be 2nxe2x88x921.
In another embodiment of the present invention, the number of the plurality of digital signal lines on one side of the output can be 2nxe2x88x922.
In yet another embodiment of the present invention, a plurality of blocking transistors are positioned between the input and selected digital signal lines, with at least one of the digital signal lines being coupled to a gate of each of the blocking transistors for controlling each of the blocking transistors.
In yet another embodiment of the present invention, a level-shifter can be positioned between selected active regions for one or more digital signal line.
The improvements set forth in these embodiments are directed primarily to conserving power and layout space.